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中文摘要：
大规模可编程逻辑器件是近年来为适应专用集成电路设计需求而迅速发展起来的一类新型可编程ASIC器件。随着它的不断应用和发展，也使电子设计的规模和集成度不断提高。随着数字电子技术的发展，数字信号处理的理论和技术也己日趋成熟，并广泛地应用于通讯、语音处理、计算机和多媒体等领域。快速傅立叶变换作为DSP的核心技术之一，其基本思想是将较长序列的离散傅立叶变换运算逐次分解为较短序列的DFT运算的一种快速算法。它使离散傅立叶变换运算时间缩短了几个数量级。FFT已经成为现代信号处理的重要理论之一。根据傅里叶变换特点，设计一种能够完成4,16,64,256或1024点复数快速傅里叶变换处理器芯片。16,64点运算采用基-4级联流水线结构,256,1024点采用二维结构,数据采用块浮点表示。使用Synopsys公司的综合及布局布线工具在SMIC CMOS 0.18μm工艺上进行ASIC实现。该处理器芯片在100MHz时钟频率连续工作时,处理一组1024点FFT序列需要24.8μs,每隔10.24μs输出一组1024点运算结果。在FFT实时硬件处理器的设计实现过程中，利用递归结构以及成组浮点制运算方式，解决了蝶形计算、数据传输和存储操作协调一致问题。合理地解决了位增长问题。同时，采用并行高密度乘法器和流水线工作方式，并将双端口RAM、只读ROM全部内置在FPGA芯片内部，使整个系统的数据交换和处理速度得以很大提高，实际合理地解决了资源和速度之间的相互制约问题。
关键词：蝶形运算；块浮点运算；快速傅立叶变换；流水线结构；可重配置
Title ASIC Design for Real-Time Reconfigurable FFT Processor
Abstract：
With the development of Application Specific Integrated Circuit, great progress has been made in program able large scale logic devices. The scale and integration of electronic system are being enlarged continuously .As the Digital Technology fast speed developed, Digital Signal Processing (DSP) have been widely used in many areas, such as communication, voice process, computer and multimedia. Fast Fourier Transform (FFT) is the core technique of DSP. The main idea of FFT is to transfer a large Discrete Fourier Transform (DFT) computation into a group of short length DFT computations. The performing time of FFT is shorter a few stages than DFT's. FFT has already played an important role in modern DSP. A complex data fast Fourier transforms(FFT) processor is proposed. This FFT processor can be reconfigured as a 4,16,64,256 or 1024 points computation.Radix-4 pipelined architecture is adopted for 16 and 64 points computation. Two-dimensional architecture is adopted for 256 and 1024 points computation .Block floating point algorithm is adopt. The ASIC design is synthesized ,placed and routed using Synopsys with SMIC CMOS 0118μm library .When the processor operates continuously at 100 MHz, it can calculate the first 1024 complex points FFT in 24.8μs, and then get 1024 results in each 10.24μs. In the course of realization, the recursive structure and group float point arithmetic operations are adopted, which can make butterfly computing, data transformation and memory coincide, and avoid the bottleneck. Array and area optimizing multipliers are used as well as pipeline pattern. Dual-RAM and ROM are built inside the system. These methods accelerate the operating and reasonably resolve the mutually restriction of resources and speed.
